1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly, to a shift register circuit having low power consumption.
2. Description of the Prior Art
Liquid crystal displays (LCDs) have advantages of a thin profile, low power consumption, and low radiation, and are broadly adopted for application in media players, mobile phones, personal digital assistants (PDAs), computer displays, and flat screen televisions. The operation of a liquid crystal display is featured by modulating voltage drops between opposite sides of a liquid crystal layer for twisting the angles of the liquid crystal molecules in the liquid crystal layer so that the transmittance of the liquid crystal layer can be controlled for illustrating images with the aid of light source provided by a backlight module. In general, the liquid crystal display comprises plural pixel units, a source driver, and a shift register circuit. The source driver is utilized for providing plural data signals to be written into the pixel units. The shift register circuit comprises a plurality of shift register stages and functions to generate plural gate signals for controlling the operations of writing the data signals into the pixel units. That is, the shift register circuit is a crucial device for providing a control of writing the data signals into the pixel units.
FIG. 1 is a schematic diagram showing a prior art shift register circuit. As shown in FIG. 1, the shift register circuit 100 comprises a plurality of shift register stages and, for ease of explanation, illustrates an (N−1)th shift register stage 111, an Nth shift register stage 112 and an (N+1)th shift register stage 113. Each shift register stage is employed to generate one corresponding gate signal furnished to one corresponding gate line according to a low power voltage Vss and a gate signal generated by the preceding shift register stage. For instance, the (N−1)th shift register stage 111 is utilized for generating a gate signal SGn−1 furnished to a gate line GLn−1 according to the low power voltage Vss and a gate signal SGn−2, the Nth shift register stage 112 is utilized for generating a gate signal SGn furnished to a gate line GLn according to the low power voltage Vss and the gate signal SGn−1, and the (N+1)th shift register stage 113 is utilized for generating a gate signal SGn+1 furnished to a gate line GLn+1 according to the low power voltage Vss and the gate signal SGn. In the operation of the Nth shift register stage 112, the pull-up unit 190 thereof has a pull-up transistor 191 which is employed to pull up the gate signal SGn according to a driving control voltage VQn. However, if the driving control voltage VQn and the gate signal SGn are both at the low power voltage Vss, a leakage current will occur to the pull-up transistor 191 following the high-level voltage of a system clock CK. The leakage current becomes even worse as the high-level voltage of the system clock CK is increased for enhancing pixel charging rate, thereby resulting in high power consumption. Besides, if the shift register circuit 100 is integrated in a display panel comprising pixel array to bring the cost down, i.e. based on a gate-driver on array (GOA) architecture, the aforementioned high power consumption will boost the temperature of the display panel, which not only degrades panel display quality but also reduces lifetime of the display panel.